In many modern data processing systems, a useful memory function may be provided by dual storage cell memories. Dual storage cell memories, whether provided as a stand-alone memory or integrated into a logic device such as a timer, microcontroller, microprocessor, or customized logic device (e.g., an ASIC), provide two memory cells for each addressable location, each of which can be independently and asynchronously accessed, relative to the other. In addition, such memories have the function where the contents of one memory cell can be transferred to the other storage memory cell at the same address, without requiring the performing of successive read and write operations upon the two locations.
An example of a conventional dual storage cell 2 is illustrated in FIG. 1, which is similar to that described in U.S. Pat. No. 4,873,665. Referring to FIG. 1, dual storage cell 2 consists of two CMOS six-transistor static memory cells T and U, configured as cross-coupled inverters as is well known in the art. For purposes of explanation herein, memory cell T has data nodes TT (true) and TC (complement) which are coupled to bit lines TB and TB.sub.--, respectively, by way of pass gates controlled by enable line TE. Similarly, memory cell U has data nodes UT (true) and UC (complement) coupled to bit lines UB and UB.sub.-- by way of pass gates controlled by enable line UE. For ease of transfer of data states, it should be noted that the polarity convention of the arrangement of FIG. 1 is such that opposite bit lines (e.g., TB and UB.sub.--) are on the same side of dual storage cell 2, with their complements (TB.sub.-- and UB) on the other side thereof.
Transfer circuitry is provided in this prior dual storage cell 2 by way of series n-channel transistor pairs, each pair coupled between a data node and ground. The gate of one of the n-channel transistor pairs is controlled by the data node of the source memory cell (i.e., the cell from which data is being transferred); the gate of the other of the n-channel transistor in the pair is controlled by a transfer signal line, either U&gt;T or T&gt;U, depending upon the direction of the transfer. For example, referring to the transfer circuitry associated with data node TT of memory cell T, n-channel transistors 6 and 8 have their source-drain paths coupled in series between data node TT and ground. Transistor 6 has its gate coupled to data node UC, and transistor 8 has its gate coupled to signal line U&gt;T.
In operation, as described in the above-cited U.S. Pat. No. 4,873,665, the data state of memory cell U may be transferred to memory cell T by the enabling of line U&gt;T to a high logic level (enable, or word line, signals UE and TE are preferably at a low logic level during this time). For the example where cell U is storing a "0" (i.e., data node UC is high) and cell T is storing a "1" (i.e., data node TT is high), both of transistors 6 and 8 will be on, to pull data node TT low and effect the transfer; during this time, since data node UT is low, the series n-channel transistor pair connected between node TC and ground is open. However, until such time as the state of memory cell T switches (i.e., until node TC is pulled high by the p-channel transistor with its gate connected node TT, which is being pulled low), p-channel transistor 4 will remain on. The series connection of p-channel transistor 4 and n-channel transistors 6 and 8, all of which are on, provide a DC current path between V.sub.cc and ground during this portion of the data transfer from cell U to cell T. The current drawn by such a path is similar to that required during an SRAM write operation, which is quite significant as is well known. It should be noted that the transfer operation preferably is performed simultaneously for a number of dual storage cells 2, generally those associated with the same byte or word address value, or a group of words which are simultaneously transferred.
As data processing systems, particularly those utilizing modern microprocessors, continue to use wider data busses (32-bit busses now being commonplace), the other components in the system also preferably operate with data words of similar size. The transfer operation described hereinabove relative to dual storage cell 2 of FIG. 1 thus is preferably performed for the number of dual storage cells 2 corresponding to the size of the data word, or to the number of bits in the several data words which are simultaneously transferred, if such is the case. However, for dual storage cell 2 described hereinabove, the DC current path between V.sub.cc and ground will, in the worst case, be simultaneously present for the number of dual storage cells 2 on the same transfer signal line. Particularly with thirty-two-bit, or wider, data words, and hence thirty-two bit or more simultaneous dual storage cell transfers, a memory incorporating dual storage cells 2 can present a significant current spike. As is well known in the art, large current spikes not only dissipate power in the system, but can also generate Ldi/dt noise in the system capable of upsetting the operation of other circuits in the system.
It is therefore an object of this invention to provide a dual storage cell having data transfer circuitry which draws reduced current.
It is a further object of this invention to provide such a dual storage cell which avoids presenting a DC current path between the power supply nodes thereof.
It is a further object of this invention to provide such a dual storage cell which allows for flexible layout in the memory device.
It is a further object of this invention to provide such a dual storage cell which may be used in stand-alone memories, or other integrated circuits, such as logic and microprocessor circuits, having memories embedded therein.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.